Pipelining a Triggered Processing Element
- Resource Type
- Conference
- Authors
- Repetti, Thomas J.; Cerqueira, Joao P.; Kim, Martha A.; Seok, Mingoo
- Source
- 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) Microarchitecture (MICRO), 2017 50th Annual IEEE/ACM International Symposium on. :96-108 Oct, 2017
- Subject
- Computing and Processing
Pipeline processing
Microarchitecture
Registers
Computer architecture
Hazards
Delays
Field programmable gate arrays
Spatial architectures
pipeline hazards
microarchitecture
design-space exploration
low-power design
- Language
- ISSN
- 2379-3155
Programmable spatial architectures composed of ensembles of autonomous fixed-ISA processing elements offer a compelling design point between the flexibility of an FPGA and the compute density of a GPU or shared-memory many-core. The design regularity of spatial architectures demands examination of the processing element microarchitecture early in the design process to optimize overall effciency.This paper considers the microarchitectural issues surrounding pipelining a spatial processing element with triggered-instruction control. We propose two new techniques to mitigate pipeline hazards particular to spatial accelerators and non-program-counter architectures, evaluating them using in-vivo performance counters from an FPGA prototype coupled with a rigorous VLSI power and timing estimation methodology. We consider the effect of modern, post-Dennard-scaling CMOS technology on the energy-delay tradeoffs and identify a set of microarchitectures optimal for both high-performance and low-power application settings. Our analysis reveals the effectiveness of our hazard mitigation techniques as well as the range of microarchitectures designers might consider when selecting a processing element for triggered spatial accelerators. CCS CONCEPTS • Computer systems organization → Pipeline computing; Reduced instruction set computing; Multiple instruction, multiple data; Multicore architectures; Interconnection architectures; • Hardware → Power and energy;