Analysis of Single Event Gate Rupture in Trench Gate SJ-VDMOS with SiO2-Si3N4 Dielectric Stacking
- Resource Type
- Conference
- Authors
- Verma, Rohit; Ranjan, Sanjeev; Naugarhiya, Alok
- Source
- 2021 IEEE Region 10 Symposium (TENSYMP) Region 10 Symposium (TENSYMP), 2021 IEEE. :1-6 Aug, 2021
- Subject
- Aerospace
Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Fields, Waves and Electromagnetics
General Topics for Engineers
Geoscience
Nuclear Engineering
Photonics and Electrooptics
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Transportation
Performance evaluation
Radiation hardening (electronics)
Stacking
Metals
Silicon nitride
Logic gates
Tools
Strike field
LET
SEGR
Silicon dioxide
EOT
SiO2-Si3N4 Stacking
- Language
- ISSN
- 2642-6102
In this proposed work, single event gate rupture (SEGR) analysis was performed on a vertical double diffused metal oxide semiconductor field effect transistor (VDMOS) where the high-energy charged particles at different locations incident normally across the device. It was observed that with the combination of SiO2-Si3N4 (30nm, 130nm) stacking, the device shows better radiation hardening towards SEGR. The equivalent oxide thickness (EOT) of the dielectric layer is considered 100nm. Ions with different Linear Energy Transfer (LET) are investigated. Silvaco ATLAS TCAD tool was used. The above-proposed technique made the device Radhard and allows it to work in high-power applications in a radiation environment.