With the evolution in technology, the introduction of a tiled chip multi-core processor (TCMP), allowed being used in a well-defined and critical system such as embedded devices and Internet-of-things (IoT). The communication between cores is carried out by a network mechanism known as NoC (Network on Chip) widely employed by multi-core architecture. An increase in demand in the market for multi-core System-on-Chip (SoC) resulted in the embedding of third-party-intellectual property (3PIP) on the chip to reduce manufacturing time constraints. But the problem with this 3PIP is whether the chip consists of additional circuitry other than its design. This additional circuitry can also refer to Hardware Trojan (HT) with the purpose of infecting the chip and disrupting its performance by performing Denial-of-service, Injection suppression, and tempering of packets, on the System. In this presented work, we propose a novel HT that can attack the network resources with the behavior to alter the status of the Virtual Channel (VC) resulting in delaying the processing of packets to its destination tile. Further, we studied the impact of the proposed HT on the performance of the system. According to experimental findings, the suggested HT can raise packet network latency by 4.4%, increase packet queuing latency by 5.3%, and injection suppression by 4%. While other parameters such as flit processed and link utilization also show a significant impact on routers and can be used to localize the HT.