Lowering Dynamic Power of a Stream-based CNN Hardware Accelerator
- Resource Type
- Conference
- Authors
- Piyasena, Duvindu; Wickramasinghe, Rukshan; Paul, Debdeep; Lam, Siew-Kei; Wu, Meiqing
- Source
- 2019 IEEE 21st International Workshop on Multimedia Signal Processing (MMSP) Multimedia Signal Processing (MMSP), 2019 IEEE 21st International Workshop on. :1-6 Sep, 2019
- Subject
- Communication, Networking and Broadcast Technologies
Computing and Processing
Signal Processing and Analysis
CNN
FPGA acclerator
low-power designs
- Language
- ISSN
- 2473-3628
Custom hardware accelerators of Convolutional Neural Networks (CNN) provide a promising solution to meet real-time constraints for a wide range of applications on low-cost embedded devices. In this work, we aim to lower the dynamic power of a stream-based CNN hardware accelerator by reducing the computational redundancies in the CNN layers. In particular, we investigate the redundancies due to the downsampling effect of max pooling layers which are prevalent in state-of-the-art CNNs, and propose an approximation method to reduce the overall computations. The experimental results show that the proposed method leads to lower dynamic power without sacrificing accuracy.