A hierarchical mathematical model for automatic pipelining and allocation using elastic systems
- Resource Type
- Conference
- Authors
- Cortadella, Jordi; Petit, Jordi
- Source
- 2017 51st Asilomar Conference on Signals, Systems, and Computers Signals, Systems, and Computers, 2017 51st Asilomar Conference on. :115-120 Oct, 2017
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Signal Processing and Analysis
Registers
Delays
Optimization
Throughput
Mathematical model
Computer architecture
- Language
- ISSN
- 2576-2303
The advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical task for the delivery of high-quality solutions. Time elasticity opens a new avenue of optimizations that can be applied after HLS and before logic synthesis, proposing new sequential transformations that expand beyond classical retiming and enlarge the register-transfer level (RTL) exploration space. This paper proposes a mathematical model for RTL transformations that exploit elasticity to select the best implementation for each functional unit and add pipeline registers to increase performance. Two simple examples are used to validate the effectiveness and potential benefits of the model.