A CPLD design of a self-organizing system for data clustering
- Resource Type
- Conference
- Authors
- Ohkubo, J.; Miyanaga, Y.; Tochinai, K.
- Source
- 1998 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and systems Circuits and Systems (ISCAS), 1998 IEEE International Symposium on. 2:441-444 vol.2 1998
- Subject
- Components, Circuits, Devices and Systems
Communication, Networking and Broadcast Technologies
Engineered Materials, Dielectrics and Plasmas
Clustering methods
Hardware
Circuits
Clustering algorithms
Costs
Field programmable gate arrays
Programmable logic arrays
Euclidean distance
Data engineering
Design engineering
- Language
A hardware design of a self-organizing system is presented in this report. A high performance parallel processor is designed with pipeline modules. The size of this system is programmable within a certain degree. In this paper, we design this system using a target CPLD. In addition, this paper shows the error analysis of floating-point operation to estimate the optimum word length of data for the minimization of circuit resources.