Controllable Inverter Delay and Suppressing Vth Fluctuation Technology in Silicon on Thin BOX Featuring Dual Back-Gate Bias Architecture
- Resource Type
- Conference
- Authors
- Tsuchiya, Ryuta; Ishigaki, Takashi; Morita, Yusuke; Yamaoka, Masanao; Iwamatsu, Toshiaki; Ipposhi, Takashi; Oda, Hidekazu; Sugii, Nobuyuki; Kimura, Shin'ichiro; Itoh, Kiyoo; Inoue, Yasuo
- Source
- 2007 IEEE International Electron Devices Meeting Electron Devices Meeting, 2007. IEDM 2007. IEEE International. :475-478 Dec, 2007
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
Inverters
Delay
Random access memory
Fluctuations
Silicon
Doping
Threshold voltage
Voltage control
Degradation
Logic devices
- Language
- ISSN
- 0163-1918
2156-017X
45 nm-gate SOTB (Silicon on Thin BOX)) technology for LSTP application has been successfully developed. In the SOTB device, short-channel effect immunity without channel doping and back-gate bias threshold voltage (V th ) control are demonstrated. GIDL is reduced with avoiding drive current and inverter delay degradation minimum by optimizing offset source/drain extension to gate overlap. We have also proposed the SOTB device design enabling the controllable inverter delay and low V th fluctuation for Logic and SRAM memory cell transistors. Inverter delay can be improved from 19.3 to 10.5 ps by applying the forward back-gate bias. Furthermore, V th fluctuation can be reduced about 16% by applying the reverse back-gate bias. A 6-transistor SRAM memory cell of the SOTB structure by adding a reverse back bias control has shown to dramatically improve SRAM memory cell stability.