Threshold-voltage anomaly in sub-0.2 /spl mu/m DRAM buried-channel pFET devices
- Resource Type
- Conference
- Authors
- Murthy, C.S.; Katsumata, R.; Inaba, S.; Rengarajan, R.; Oldiges, P.; Ronsheim, P.
- Source
- 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) VLSI technology, systems, and applications VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on. :19-22 2001
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Signal Processing and Analysis
Random access memory
Implants
Doping profiles
Electric potential
Joining processes
Potential well
Equations
Neodymium
Charge carrier processes
- Language
- ISSN
- 1524-766X
Measurements and simulation have been used to study threshold-voltage (V/sub t/) dependence on gate oxide thickness (t/sub ox/) for long-channel buried-channel (BC-) pFET devices in sub-0.2 /spl mu/m CMOS technologies. The combination of the dual gate oxide process using N/sub 2/ implantation to create the thinner gate oxide and well RTA results in the thinner t/sub ox/ devices having higher V/sub t/, contrary to expectation (V/sub t/-t/sub ox/ anomaly). Detailed analysis of doping profiles, depletion contours, and electric potential confirms this anomaly both in the enhancement and depletion modes of operation. These studies show that a balance of net doping between that near the surface and that around the BC-layer is a stringent requirement for the Vt control in BC-pFETS.