Robustness study of 1700 V 45 mΩ SiC MOSFETs
- Resource Type
- Conference
- Authors
- Molin, Quentin; Kanoun, Mehdi; Raynaud, Christophe; Morel, Herve
- Source
- 2018 IEEE International Conference on Industrial Technology (ICIT) Industrial Technology (ICIT), 2018 IEEE International Conference on. :830-834 Feb, 2018
- Subject
- Aerospace
Components, Circuits, Devices and Systems
Computing and Processing
Engineering Profession
Fields, Waves and Electromagnetics
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Transportation
Aging
Temperature measurement
Logic gates
MOSFET
Threshold voltage
Silicon carbide
Reliability
Silicon Carbide MOSFET
threshold voltage instability
gate bias stress
robustness
Keysight B1506A
JEDEC
reliability testing
- Language
The threshold voltage instability is a main reliability issue of Silicon Carbide MOSFET transistors. It is a critical parameter when it comes to give a failure in time rate for industrial power applications. In this context, a static ageing test based on JEDEC standard is proposed and the resulting gate oxide degradation is studied and discussed in this paper. Complementary testing was performed with dynamic reliability on the gate and the results obtained are used to add insight to the current discussion of SiC MOSFET reliability standards. Additionally, test bench and characterization protocols are detailed.