As device dimensions shrink, the use of ELK dielectric becomes crucial for reducing interline capacitance and RC delay. However, ELK dielectric materials are susceptible to mechanical stress, leading to potential cracks. CPI, resulting from CTE mismatch between die and substrate, can introduce thermal load directly onto ELK layers and cause crack formation and propagation. In this paper, the finite element simulation method is applied to investigate ELK layer stress during the cooling stage of the solder reflow process. Impacts of various parameters on ELK layer stress are analyzed. The results indicate that the mechanical properties of bump solder have a significant impact on the local stress of ELK layer. Additionally, the height of bump solder cap, bump pitch and the thickness of PI layer are also assessed as variables influencing the ELK layer stress. After the parameter optimization, the maximum value of the equivalent plastic strain of solder and the tensile stress of ELK dielectric layer are effectively reduced by 34% and 40% respectively.