Delay test of chip I/Os using LSSD boundary scan
- Resource Type
- Conference
- Authors
- Gillis, P.; Woytowich, F.; McCauley, K.; Baur, U.
- Source
- Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270) International test conference Test Conference, 1998. Proceedings., International. :83-90 1998
- Subject
- Components, Circuits, Devices and Systems
Signal Processing and Analysis
Power, Energy and Industry Applications
Circuit testing
Logic testing
Switches
Software testing
Automatic testing
Delay effects
Driver circuits
Packaging
Latches
Performance evaluation
- Language
- ISSN
- 1089-3539
This paper describes a novel design-for-test (DFT) concept for I/O delay testing while contacting very few pads, using boundary scan and new test-generation software. In production testing of the IBM System/390 Generation 3/sup TM/ and several ASIC chips, these patterns uncovered unique manufacturing defects.