Practical Aspects of Delay Testing for Nanometer Chips
- Resource Type
- Conference
- Authors
- Chickermane, V.; Keller, B.; McCauley, K.; Uzzaman, A.
- Source
- 14th Asian Test Symposium (ATS'05) Test Symposium, 2005. Proceedings. 14th Asian. :470-470 2005
- Subject
- Components, Circuits, Devices and Systems
Signal Processing and Analysis
Power, Energy and Industry Applications
Timing
Logic testing
Delay effects
System testing
Clocks
Nanoscale devices
Test pattern generators
Automatic testing
Automatic test pattern generation
Bridges
- Language
- ISSN
- 1081-7735
2377-5386
As SoC feature sizes are moving down to the nanometer range there is an increasing need to develop high quality, cost-effective and sensitive tests for nanometer devices. Many of the newer defects like resistive vias and bridges exhibit defective timing behavior, and require the usage of the transition fault model and sophisticated control of the launch-to-capture timings to the equivalent of system speeds.