Serial data link interface for memory applications
- Resource Type
- Conference
- Authors
- Madany, Waleed; Rashdan, Mostafa; Hasaneen, El-Sayed
- Source
- 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) Circuits and Systems (MWSCAS), 2016 IEEE 59th International Midwest Symposium on. :1-4 Oct, 2016
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Photonics and Electrooptics
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Clocks
Timing
Receivers
Demodulation
Jitter
Transmitters
SerDes
Time-Based Architecture
Time-to-Digital Converter(TDC) Circuit
Pulse-Position Modulation(PPM)
Pulse-Amplitude Modulation(PAM)
Memory Interface
- Language
- ISSN
- 1558-3899
A time-based serial data link architecture utilizing Pulse-Amplitude Modulation (PAM) technique combined with Pulse-Position Modulation (PPM) technique is presented in this paper. The proposed time-based link combines the PAM technique with the PPM technique in order to increase the number of transmitted bits per symbol without altering the bandwidth of the transmitted signal. The proposed timing correction technique used at the receiver side allows increasing the total number of the AM transmitted bits per symbol without affecting the recovery of the pulse-position modulation bits. The proposed link can replace the SerDes link in transmitting high speed data in modern mobile memory architectures in order to relax the interface design while using low frequency clock signal. A 5-bit 4-Gb/s serial data link has been designed and simulated in 130 nm CMOS technology using 800 MHz as a clock signal. A 2.5 inch Fr4 channel has been used as a transmission media in order to evaluate the link performance for mobile memory applications. The power consumption of the designed link is less than 84 mW.