Yield-award placement optimization for Switched-Capacitor analog integrated circuits
- Resource Type
- Conference
- Authors
- Huang, Chien-Chih; Chen, Jwu-E; Luo, Pei-Wen; Wey, Chin-Long
- Source
- 2011 IEEE International SOC Conference SOC Conference (SOCC), 2011 IEEE International. :170-173 Sep, 2011
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Communication, Networking and Broadcast Technologies
Capacitors
Layout
Correlation
Optimization
Wires
Parasitic capacitance
Yield-Award
random variation
spatial correlation
physical realization
layout generator
- Language
- ISSN
- 2164-1676
2164-1706
Paralleling square unit capacitors have been commonly used for Switched-Capacitor circuits to achieve higher accurate capacitor ratio. However, the capacitor ratio may be shifted due to the wire interconnection of these unit capacitors. The small capacitor ratio shift may cause a significant yield drop. The ratio shift can be reduced by using extra circuitry to achieve parasitic insensitive design. This study presents a simple a layout modification to alleviate the ratio shift, thus enhancing yield, without requiring extra circuitry.