Back gate impact on the noise performances of 22FDX fully-depleted SOI CMOS
- Resource Type
- Conference
- Authors
- Kane, Ousmane Magatte; Lucci, Luca; Scheiblin, Pascal; Poiroux, Thierry; Barbe, Jean-Charles; Danneville, Francois
- Source
- 2020 15th European Microwave Integrated Circuits Conference (EuMIC) Microwave Integrated Circuits Conference (EuMIC), 2020 15th European. :81-84 Jan, 2021
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Fields, Waves and Electromagnetics
Photonics and Electrooptics
Performance evaluation
Microwave measurement
Voltage measurement
Silicon-on-insulator
Logic gates
Noise measurement
Gain
CMOS
FDSOI
back gate
22FDX
noise measurement
millimeter wave
- Language
Ultra-Thin-Body and Back-oxide Fully-Depleted Silicon-On-Insulator (UTBB-FDSOI) MOSFETs are the most recent and advanced Silicon-On-Insulator (SOI) architecture proposed to overcome the down-scaling limitations of traditional bulk devices. The UTBB-FDSOI architecture has already been proved very attractive for RF-mmW circuits thanks to the excellent reported RF figure of merits (FOMs). In this article, we report on an experimental investigation of the back gate biasing impact on the high-frequency (HF) noise performances of an advanced 22 nm UTBB-FDSOI technology developed by GLOBALFOUNDRIES. For the lower gate voltages, the back gate biasing was shown to decrease by one third the equivalent noise resistance (Rn). Moreover, a 3 dB increase for the associated gain (Ga) was achieved at Vg=0.3V. A relaxed contacted-poly-pitch was also shown to decrease Rn by 11%.