22FDX® fMAX Optimization through Parasitics Reduction and GM Boost
- Resource Type
- Conference
- Authors
- Zhao, Zhixing; Lehmann, Steffen; Lucci, Luca; Andee, Yogadissen; Divay, Alexis; Pirro, Luca; Herrmann, Tom; Zaka, Alban; Sousa, Ricardo; Artz, Patrick James; Hempel, Klaus; Faul, Juergen; Chen, Tianbing; Taylor, Richard; Mazurier, Jerome; Grass, Carsten; Hoentschel, Jan; Harame, David
- Source
- ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC) Solid-State Device Research Conference (ESSDERC), 2019 49th European. :166-169 Sep, 2019
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
General Topics for Engineers
Photonics and Electrooptics
Power, Energy and Industry Applications
RF
FDSOI
FMAX
FT
GATE RESISTANCE REDUCTION
PARASITIC CAPACITANCE REDUCTION
- Language
- ISSN
- 2378-6558
This paper proposes three methods of reducing device gate resistance and parasitic capacitance while boosting transconductance of MOSFET on 22FDX ® . The f MAX can be improved by 50% and up to 75% for NFET and PFET with respect to a standard 2.0µm finger width layout, respectively.