We report on a major advancement in full-field EUV Lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186μm 2 6T-SRAMs, with W-filled contacts. Alignment to other 193nm immersion litho levels shows very good overlay values ≤20nm. Other key features of the process are: 1) use of high-k/Metal Gate FinFETs with good gate CD control: 3σ≤7nm after double-dipole 193nm immersion litho (NA=0.85) and 3σ≤9nm after double-Hard Mask gate etch; and 2) use of an ultra-thin NiPt-silicide for S/D and an optimized spacers module without Si recess at dense FINs pitch. Excellent SRAM V DD scalability down to 0.6V (SNM≫0.1V DD ) and healthy electrical characteristics (V T , σ(ΔV T ), I-V) for the cell transistors are obtained.