We have studied the performance of double-quantum-barrier $[\hbox{TaN}- \hbox{Ir}_{3}\hbox{Si}]-[\hbox{HfAlO}-\hbox{LaAlO}_{3}]-\break \hbox{Hf}_{0.3}\hbox{N}_{0.2}\hbox{O}_{0.5}-[ \hbox{HfAlO}-\hbox{SiO}_{2}]$ -Si charge-trapping memory devices. These devices display good characteristics in terms of their $\pm$ 9-V program/erase (P/E) voltage, 100- ${\rm \mu}\hbox{s}$ P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 $^{\circ} \hbox{C}$. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced interface trap generation.