A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS
- Resource Type
- Conference
- Authors
- Prinzie, Jeffrey; Kulis, Szymon; Leitao, Pedro; Francisco, Rui; De Smedt, Valentijn; Moreira, Paulo; Leroux, Paul
- Source
- 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Circuits & Systems (LASCAS), 2019 IEEE 10th Latin American Symposium on. :63-66 Feb, 2019
- Subject
- Components, Circuits, Devices and Systems
Signal Processing and Analysis
Voltage-controlled oscillators
Delays
Tuning
Detectors
Jitter
Radiation hardening (electronics)
Feeds
CDR
Single-Event Upsets
Radiation hardening
jitter
phase noise
clock recovery
- Language
- ISSN
- 2473-4667
A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for high-energy physics and space applications. The CDR employs a novel soft-error tolerant Voltage Controlled Oscillator (VCO) and includes a high-speed feed-forward path to stabilize the CDR to compensate for an additional pole in the VCO to harden it against ionizing particles. The CDR has a data rate of 2.56 Gbps and uses In-Phase/Quadrature (IQ) clocks in combination with a frequency detector (FD) to increase the pull-in range. The circuit was designed in a 65 nm CMOS technology and has a core power consumption of only 34 mW.