Wafer-Level Aging of InGaAs/GaAs Nano-Ridge p-i-n Diodes Monolithically Integrated on Silicon
- Resource Type
- Conference
- Authors
- Hsieh, Ping-Yi; Tsiara, Artemisia; O'Sullivan, Barry; Yudistira, Didit; Baryshnikova, Marina; Groeseneken, Guido; Kunert, Bernardette; Pantouvaki, Marianna; Campenhout, Joris Van; De Wolf, Ingrid
- Source
- 2022 IEEE International Reliability Physics Symposium (IRPS) Reliability Physics Symposium (IRPS), 2022 IEEE International. :9A.3-1-9A.3-9 Mar, 2022
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Degradation
Heating systems
Semiconductor device reliability
Sintering
Aging
Reliability engineering
Silicon
Monolithic integration
Nano-ridge engineering
Stress-induced degradation
Silicon photonics
III-V p-i-n diode
- Language
- ISSN
- 1938-1891
For the first time, a reliability study on degradation of InGaAs/GaAs nano-ridge p-i-n diodes monolithically integrated on Si by nano-ridge engineering (NRE) is reported. Wafer-level constant current stress in forward bias shows a gradual power law aging of both forward and dark current. Current crowding and Joule heating near the p-contact are responsible for the degradation in forward bias region. Indications of defect formation and Ti diffusion at the metal/GaAs interface are witnessed. The electrical stress-induced leakage current builds up at reverse bias region, pointing to the degradation of crystal quality. A sintering process lowers the p-contact resistance and improves electrical stability. The high aspect-ratio of the trenches leads to effective threading dislocation trapping: no dislocations have been observed to penetrate the active region during the 5000s stress time. This early work sheds light on realizing electrically robust GaAs diodes on Si and reliable monolithic lasers.