Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking—Part I: Constant Input
- Resource Type
- Periodical
- Authors
- Fitzgibbon, B.; Kennedy, M. P.; Maloberti, F.
- Source
- IEEE Transactions on Circuits and Systems I: Regular Papers IEEE Trans. Circuits Syst. I Circuits and Systems I: Regular Papers, IEEE Transactions on. 58(9):2137-2148 Sep, 2011
- Subject
- Components, Circuits, Devices and Systems
Delta-sigma modulation
Quantization
Multi-stage noise shaping
Hardware
Noise cancellation
Design methodology
Bus-splitting
digital delta-sigma modulator (DDSM)
dither
nesting
- Language
- ISSN
- 1549-8328
1558-0806
In this two-part paper, a design methodology for bus-splitting digital delta-sigma modulators (DDSMs) is presented. The design methodology is based on error masking and is applied to both ditherless and dithered DDSMs with constant and sinusoidal inputs. Rules for selecting the appropriate wordlengths of the constituent DDSMs are derived which ensure that the spectral performance of the bus-splitting architecture is comparable to that of the conventional design but with less hardware. Behavioral simulations and experimental results confirm the theoretical predictions. Part I addresses ditherless MASH DDSMs with constant inputs; Part II focuses on DDSMs with dither and sinusoidal inputs.