Analog Deep Neural Network Based on NOR Flash Computing Array for High Speed/Energy Efficiency Computation
- Resource Type
- Conference
- Authors
- Xiang, Y. C.; Huang, P.; Zhou, Z.; Han, R. Z.; Jiang, Y. N.; Shu, Q. M.; Su, Z. Q.; Liu, Y. B.; Liu, X. Y.; Kang, J. F.
- Source
- 2019 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 2019 IEEE International Symposium on. :1-4 May, 2019
- Subject
- Bioengineering
Components, Circuits, Devices and Systems
Power, Energy and Industry Applications
Signal Processing and Analysis
Hardware
Convolution
Energy consumption
Task analysis
Programming
Guidelines
Neural networks
computing in memory
NOR Flash Computing Array
hardware implementation
analog deep neural network
- Language
- ISSN
- 2158-1525
In this paper, a novel hardware implementation of analog deep neural network (DNN) based on NOR Flash Computing Array (NFCA) is presented. The approach eliminates additional analog-to-digital/digital-to-analog (AD/DA) conversion between adjacent layers. Applied to the MNIST recognition task, the simulations indicate that the designed DNN based on the novel implementation approach has the excellent performance such as the time delay of 3×10 −7 s and energy consumption of 1.97×10 −8 J per image, which brings 8× and 123× enhancements compared to the conventional digital scheme. The NFCA based analog DNN also saves 86.4% of area. All of the improvements benefit from the analog-signal based scheme. The proposed high speed and energy efficient hardware implementation would be promising in terms of artificial intelligence (AI) at the edge.