Digitally-assisted analog and analog-assisted digital design techniques for a 28 nm mobile System-on-Chip
- Resource Type
- Conference
- Authors
- Jiang, Xicheng; Ramachandran, Narayan Prasad; Kang, Dae Woon; Chen, Chee Kiong; Rutherford, Mark; Cong, Yonghua; Chang, David
- Source
- ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th. :475-478 Sep, 2014
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Engineering Profession
General Topics for Engineers
Power, Energy and Industry Applications
Signal Processing and Analysis
Temperature measurement
Program processors
System-on-chip
Clocks
Monitoring
Temperature sensors
Resistors
Analog-assisted digital technique
Digitally-assisted analog technique
Switching regulator
PVT monitor
DVFS
AVS
All-digital CDR
Intra-bit boosting
Multicore processor
- Language
- ISSN
- 1930-8833
A 28 nm 4G/LTE mobile System-on-Chip (SoC) with digitally-assisted analog and analog-assisted digital design techniques is presented. Multicore processors with integrated switching regulators achieve 1.8 GHz and 1.5 GHz speeds for A15 and A7 processors, respectively. The multiphase integrated switching regulator achieves 90% efficiency and up to 8A current capability. PVT monitors enable DVFS and AVS to further improve system efficiency. The all-digital CDR achieves state-of-the-art FOMs at 0.208 mW/Gb/s and 468.75 µm 2 /Gb/s. An intra-bit boosting technique helps the USB2.0 TX meet the eye mask with a 200 ps margin and reduced rise and fall times.