Invited: An Active Filter Balun and Frequency Doubler for Parametric Phase Noise Reduction Systems
- Resource Type
- Conference
- Authors
- Gourousis, Thomas; Yan, Mengting; Hussein, Hussein M. E.; Cassella, Cristian; Rinaldi, Matteo; Onabajo, Marvin
- Source
- 2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS) Circuits and Systems (MWSCAS), 2023 IEEE 66th International Midwest Symposium on. :424-428 Aug, 2023
- Subject
- Components, Circuits, Devices and Systems
Phase noise
Varactors
Semiconductor device modeling
Baluns
Active filters
System-on-chip
Tuning
Active balun
frequency doubler
phase noise reduction system
parametric circuits
radio frequency circuits
- Language
- ISSN
- 1558-3899
This paper introduces an active filter balun and frequency doubler intended for an on-chip parametric phase noise reduction system. The 2.4 GHz balun is designed with inductor-capacitor (LC) tanks to provide narrowband filtering. This architecture also leads to low amplitude and phase errors of the differential outputs by relying on the matching of passive devices in the two branches. The frequency doubler utilizes a push-push structure to enhance the second harmonic at its output. An analysis has been completed for optimization of its performance and to identify design tradeoffs. Tuning varactors have been included in the design to alleviate the deviation of the resonance frequency of the LC tanks in process corners. The balun and doubler circuits were designed in a standard 65 nm CMOS process with a 0.6V power supply, consuming 450 μW. According to simulations, the active filter balun has a 1.2 degree phase mismatch and a 1.3% amplitude mismatch in the typical corner, and respective errors less than -3 to 4 degrees and -2% to 3% across corner and mismatch simulations. The doubler is able to provide a signal with its highest harmonic at 40 dB below the desired 4.8 GHz output component.