An X-Band Quadruple Frequency Multiplier in 65-nm CMOS Process
- Resource Type
- Conference
- Authors
- Guo, Haiqiang; Pang, Dongwei; Wu, Shiwei; Sun, Liguo
- Source
- 2022 Cross Strait Radio Science & Wireless Technology Conference (CSRSWTC) Cross Strait Radio Science & Wireless Technology Conference (CSRSWTC), 2022. :1-3 Dec, 2022
- Subject
- Computing and Processing
Fields, Waves and Electromagnetics
Photonics and Electrooptics
Signal Processing and Analysis
Wireless communication
RNA
Power amplifiers
Bandwidth
Voltage
Harmonic analysis
Frequency conversion
CMOS
frequency multiplier
doubler
X-band
harmonic suppression
- Language
- ISSN
- 2377-8512
This paper proposes an X-band quadruple frequency multiplier using 65-nm CMOS technology. The quadruple frequency multiplier consists of two stages of doublers and one stage of the drive amplifier. The quadruple frequency multiplier achieves the conversion gain of 5 dB and the maximum output power of 6 dBm with an output signal frequency range of 8–10 GHz. Harmonic rejections are over 25 dBc in the entire bandwidth. The circuit consumes 19.2 rnA at a supply voltage of 1 V and occupies an area of $\boldsymbol{1.12 \text{mm} \times 0.44 \text{mm}}$ without pads.