Chip-Level ESD Verification Using Graph-Theory Based Approach
- Resource Type
- Conference
- Authors
- Galic, Vlatko; Wieers, Aarnout; Gillon, Renaud; Baric, Adrijan
- Source
- 2019 International Symposium on Electromagnetic Compatibility - EMC EUROPE Electromagnetic Compatibility - EMC EUROPE, 2019 International Symposium on. :875-880 Sep, 2019
- Subject
- Aerospace
Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Fields, Waves and Electromagnetics
Power, Energy and Industry Applications
Transportation
Electrostatic discharges
Computational modeling
Integrated circuit modeling
Tools
Transmission line matrix methods
Resistors
ESD
full-chip simulations
bipolar technology
ESD verification
graph theory
ESD current paths
- Language
- ISSN
- 2325-0364
An Electrostatic Discharge (ESD) simulation and verification flow that has been demonstrated on a real design in bipolar technology is presented in this work. The described flow can be used to verify the level of ESD robustness of integrated circuit (IC) designs. Secondly, it is possible to identify the ESD current paths between any two nodes in the design, and the flow can determine which devices will fail in the case of a catastrophic ESD event. The presented flow is based on a graph-theory Floyd-Warshall algorithm and previously defined breaking voltage (BV) models.