Low-power and small-area implementations are essential in the mobile-phone market. Serial signal-processing architectures, in which signal-processing circuits such as a programmable-gain amplifier (PGA) and an ADC can be shared by column-level correlated double sampling (CDS) circuits [1–5], promise to reduce chip size and power consumption. However, conventional column CDS circuits composed of linear capacitors or NMOS capacitors (NMOSCAPs) with output buffers (OBUFs) still occupy a large footprint [2–5]. In this work, to reduce the area and the power consumption of column CDS circuits while keeping high linearity, 1.5V PMOS capacitors (PMOSCAPs) are employed. These capacitors work as low-cost sample-and-hold (S/H) capacitors as well as voltage level-shifters by using body-terminal control. To reduce the power consumption of the ADC, instead of a conventional pipeline ADC [3–5], we propose a 10b self-differential offset-cancelled pipeline SAR-ADC. It operates with the reference voltage of the ADC's half full-scale voltage (V fs ), leading to a reduction of 80% switching power and 50% capacitor DAC (CDAC) area in the ADC. A black-level correction function is built in the ADC without any additional DACs. The proof-of-concept circuits are implemented in a 1.4Mpixel CMOS image sensor that consumes 51.0mW with a frame rate of 17fps and a read noise of 187.5µV rms at 8.1× analog gain.