DAQ and control systems for the CMS global calorimeter trigger matrix processor
- Resource Type
- Conference
- Authors
- Foudas, Costas; Jones, John; Stettler, Matthew
- Source
- 2008 IEEE Nuclear Science Symposium Conference Record Nuclear Science Symposium Conference Record, 2008. NSS '08. IEEE. :3283-3286 Oct, 2008
- Subject
- Nuclear Engineering
Power, Energy and Industry Applications
Fields, Waves and Electromagnetics
Engineered Materials, Dielectrics and Plasmas
Signal Processing and Analysis
Bioengineering
Data acquisition
Control systems
Collision mitigation
Mesons
Field programmable gate arrays
Switches
Standards development
Solenoids
Backplanes
Instruments
CMS
GCT
μTCA
- Language
- ISSN
- 1082-3654
A new trigger component based on the micro-TeleCommunications Architecture (μTCA) standard is being developed for the Compact Muon Solenoid (CMS) Global Calorimeter Trigger (GCT). The new system is designed to handle the exchange of data between the GCT and the Global Muon Trigger and is called the GCT Muon and Quiet Bit System. It consists of a uTCA crate with a custom backplane instrumented with several Matrix processor cards, which use a Xilinx Virtex-5 FPGA and an M21141 72x72 cross-point switch. We discuss the development and use of the various communication systems available for the Matrix processor. Given the nature of the Virtex-5 FPGAs used as the basis of the design, there are several communication protocols available. In this paper we focus on the use of PCI express and Gigabit Ethernet UDP/IP using the built-in Virtex-5 interfaces, and TCP/IP and IPMB via an NXP microcontroller interface on the Matrix board itself. The use of these interfaces for slow control of the board and fast Data AcQuisition (DAQ) are discussed in terms of available bandwidth and resource usage. Furthermore we discuss the implications of the use of such industry-standard interfaces as a replacement for more traditional simplex busses such as VME. To that end we outline the development of a new Hardware Abstraction Layer (HAL) with built-in overlapped I/O and one possible serial bus architecture providing a metastability-tolerant interface and auto-discovery for ease of use.