A 66-MHz configurable secondary cache controller with primary cache copyback support
- Resource Type
- Conference
- Authors
- Reed, P.; Alexander, M.; Beavers, B.; Evers, R.; Gary, S.; Gerosa, G.; Grossman, A.; Gutierrez, C.; Jackson, G.; Kearney, M.; Lewelling, R.; Slaton, J.; Stanphill, R.
- Source
- 1992 Symposium on VLSI Circuits Digest of Technical Papers VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on. :16-17 1992
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Signal Processing and Analysis
Logic arrays
CMOS logic circuits
Logic devices
Random access memory
Size control
Control systems
Clocks
Microprocessors
CMOS process
Conductivity
- Language
The authors describe a 66-MHz secondary cache controller which supports a primary cache operating in copyback mode. The device integrates a 278-kb direct-mapped cache tag array plus control logic to provide full multiprocessing capability and is configurable to support cache sizes from 256 kbytes to 1 Mbyte. Implemented in a 0.8- mu m twin-well double-poly triple-metal CMOS process, the device uses a high-resistivity poly load memory cell to achieve high density.ETX