Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip
- Resource Type
- Conference
- Authors
- Beneventi, Francesco; Bartolini, Andrea; Vivet, Pascal; Dutoit, Denis; Benini, Luca
- Source
- 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014. :1-4 Mar, 2014
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Temperature sensors
Heating
Temperature measurement
Three-dimensional displays
Silicon
- Language
- ISSN
- 1530-1591
1558-1101
High temperature is one of the limiting factors and major concerns in 3D-chip integration. In this paper we use a 3D test chip (WIDEIO DRAM on top of a logic die) equipped with temperature sensors and heaters to explore thermal effects. We correlated real temperature measurements with the power dissipated by the heaters using model learning techniques. The resulting compact thermal model is able to predict temperatures at chip locations far from the temperature sensors and to infer the power dissipation at any location of the chip. Results are verified by mean of an off-sample validation technique and show a high accuracy of the compact thermal model when compared with silicon measurements.