Limits of integrated-circuit manufacturing
- Resource Type
- Periodical
- Authors
- Doering, R.; Nishi, Y.
- Source
- Proceedings of the IEEE Proc. IEEE Proceedings of the IEEE. 89(3):375-393 Mar, 2001
- Subject
- General Topics for Engineers
Engineering Profession
Aerospace
Bioengineering
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
Geoscience
Nuclear Engineering
Robotics and Control Systems
Signal Processing and Analysis
Transportation
Power, Energy and Industry Applications
Communication, Networking and Broadcast Technologies
Photonics and Electrooptics
Semiconductor device manufacture
Pulp manufacturing
Steady-state
Manufacturing processes
CMOS process
Circuits
Semiconductor devices
Material properties
Costs
Instruments
- Language
- ISSN
- 0018-9219
1558-2256
A methodology is suggested for the study of integrated-circuit manufacturing limits. It is based on a hierarchical view of manufacturing detractors and associates limits with levels in this hierarchy. The methodology is illustrated with examples of steady-state, theoretical, and process limits at today's state of the art as well as example projections to future manufacturing at what may be near the limits of complementary metal-oxide-semiconductor (CMOS) scaling. There are also some speculations on possibilities beyond these limits.