Capacitive Synaptor With Overturned Charge Injection for Compute-in-Memory
- Resource Type
- Periodical
- Authors
- Kim, C.; Phadke, O.; Kim, T.; Kim, M.; Yu, J.; Yoo, M.; Choi, Y.; Yu, S.
- Source
- IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 45(5):929-932 May, 2024
- Subject
- Engineered Materials, Dielectrics and Plasmas
Components, Circuits, Devices and Systems
In-memory computing
Capacitance-voltage characteristics
Logic gates
Flash memories
Capacitance
Temperature measurement
Junctions
Compute-in-memory
floating gate
capacitive synapse
cycling endurance
retention
- Language
- ISSN
- 0741-3106
1558-0563
A capacitive synaptic transistor (synaptor) compatible with the fabrication process of conventional Flash memory is proposed for compute-in-memory (CIM) array cells to support energy-efficient inference operations. This synaptor demonstrates the highly reliable endurance characteristic of program/erase (P/E) due to overturned charge injection occurring between a control gate (CG) and a floating gate (FG) rather than between the FG and a channel. On- and off- state capacitances ( ${C}_{\text {on}}$ and ${C}_{\text {off}}{)}$ are determined by the area ratio of CG and FG. After optimizing the pulse conditions, we achieved the P/E endurance of at least 107 cycles and retention time of 104 sec.