In the last few years, with the fleeting progress of quantum computer the traditional encryption technology is being threatened. Lattice based cryptography is a new post quantum cryptography which has been proved the security under the quantum computer attack. However, due to the limitation of communication frequency and power consumption, it is difficult to implement the lattice based cryptographic algorithm on the existing general processor platform. The polynomial multiplication is the most basic and critical operation in these lattice based cryptographic systems. It is also the computationally intensive operation which is more suitable for hardware implement. In this paper, we proposed a small area, low-power polynomial multiplier design in a specific field. Our scheme not only ensures the performance requirements, but also reduces the overhead of area and power consumption. The proposed scheme in this paper need not use the DSP resources on FPGA so that we can maximize the parallel NTT butterfly operators to improve the computing efficiency. It is a low-cost, high-performance implementation scheme.