A High Speed Extension Field Multiplier for Pairing Acceleration
- Resource Type
- Conference
- Authors
- Su, Guantong; Wu, Xingjun; Bai, Guoqiang
- Source
- 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Electron Devices and Solid-State Circuits (EDSSC), 2019 IEEE International Conference on. :1-3 Jun, 2019
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
Power, Energy and Industry Applications
pairing computation
residue number system
hardware implementation
- Language
In this paper, we present a high performance extension field multiplier for pairing acceleration on reconfigurable device. It is shown that combining Residue Number System (RNS), which is designed for concurrent architecture and modern FPGA programmable logic array. The parallelism of RNS can be fully exploited. The proof of concept is implemented on a Xilinx Ultrascale $+FPGA$, which takes 352 DSPs and accomplish a $F_{p^{6}}$ multiplication in 44 cycles at a $500MHz$ clock frequency.