Randomized Bulk-Voltages: A Countermeasure to Mask Side-Channel Leakage of CMOS Logic Gates
- Resource Type
- Conference
- Authors
- Amble, Magnus; Aunet, Snorre; Wisland, Dag T.; Kjelgard, Kristian G.
- Source
- 2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS) Circuits and Systems (MWSCAS), 2023 IEEE 66th International Midwest Symposium on. :708-712 Aug, 2023
- Subject
- Components, Circuits, Devices and Systems
Semiconductor device modeling
Analytical models
Logic gates
CMOS technology
Transistors
Leakage currents
Integrated circuit modeling
side-channel attacks
leakage power based analysis attacks
countermeasures
cryptographic circuits
- Language
- ISSN
- 1558-3899
Integrated Cryptographic Circuits implemented in Complementary Metal Oxide Semiconductor (CMOS) technology have proven to be vulnerable to static power analysis attacks. In this paper we explore the limitations of a countermeasure against leakage based power analysis attacks called Exhaustive Logic Balancing, which demonstrates complete input-independence in ideal simulations but loses it in the presence of mismatch. We propose a solution to address this input-dependency by introducing input-independent noise through randomized variations in the bulk-voltages of the logic gate's internal transistors. Simulations show that this method can conceal input-dependency in the power consumption by introducing noise with a larger magnitude than the variations in current caused by mismatch, and thus decreasing an attacker's signal-to-noise-ratio significantly in the event of a power analysis attack.