High performance Cu/low-k interconnect strategy beyond 10nm logic technology
- Resource Type
- Conference
- Authors
- Kim, R.-H.; Kim, B. H.; Kim, J. N.; Lee, J. J.; Baek, J. M.; Hwang, J. H.; Hwang, J.; Chang, J.; Yoo, S. Y.; Yim, T.-J.; Chung, K.-M.; Park, K. H.; Oszinda, T.; Kim, I S.; Lee, E. B.; Nam, S. D.; Jung, S.; Cho, Y. W.; Choi, H. J.; Kim, J. S.; Ahn, S. H.; Park, S. H.; Yoon, B. U.; Ku, J.-H.; Paak, S. S.; Lee, N.-I.; Choi, S.; Kang, H.-K.; Jung, E. S.
- Source
- 2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM), 2015 IEEE International. :1-4 May, 2015
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Robustness
Scanning electron microscopy
Resistance
Performance evaluation
Failure analysis
Metals
Ru liner for Cu reflow
ultra-low-k dielectrics
electro migration
time dependent dielectric breakdown
- Language
- ISSN
- 2380-632X
2380-6338
CVD-Ru based reflow Cu scheme demonstrates robust gap fill performance at 10nm and 7nm node equivalent patterns. Potential EM and TDDB reliability concerns associated with Ru CMP are identified and successfully addressed by the application of new processes and materials. This suggests our proposed scheme can be one of promising candidates for 10nm node logic device and beyond.