Implementation design of pulse coded neural network neuron into field programmable gate array device
- Resource Type
- Conference
- Authors
- Sevcik, P.
- Source
- 2006 International Conference on Applied Electronics Applied Electronics, 2006. AE 2006. International Conference on. :197-200 Sep, 2006
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Neural networks
Neurons
Field programmable gate arrays
Joining processes
Equations
Pixel
Pulse generation
Mathematical model
Biological system modeling
Brain modeling
- Language
This paper presents implementation design of pulse coded neural network neuron. This implementation is targeted for filed programmable gate array (FPGA) device. Comparison between this FPGA implementation and the Matlab model is presented in the end of paper.