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요약정보
基于FPGA的改进单比特接收机门限设计方法研究 / An Improved Threshold Algorithm Based on FPGA for Monobit Receivers
Resource Type
Academic Journal
Authors
刘喜洋
;
余建宇
;
陈威
;
谢煜晨
;
LIU Xiyang
;
YU Jianyu
;
CHEN Wei
;
XIE Yuchen
Source
火控雷达技术 / Fire Control Radar Technology
. 52(1):82-86
Subject
单比特接收机
CA-CFAR
补偿矩阵
FPGA
Language
Chinese
ISSN
1008-8652
Online Access
Find it @ DONGA
초록
与传统数字接收机相比,单比特数字接收机具有大带宽和快速运行的优势.这些优势归功于低比特模拟-数字(A/D)转换和简化的傅里叶变换的使用,它减少了相关的操作过程,降低了计算负担,使单比特数字接收器能够快速响应.然而,这种用法缩小了单比特数字接收器的双信号动态范围,限制了其在双信号检测中的应用.为了解决这个问题,在单比特接收机中引入了单元平均恒虚警(CA-CFAR)算法,并结合现有的补偿矩阵算法提出了一种新的自适应阈值处理方法,以提高单比特数字接收机在双信号检测中的性能.仿真结果表明,所提出的方法可以有效拓宽双信号动态范围,提高双信号检测的成功率.此外,还进行了FPGA仿真以证明该算法的可实现性,为单比特接收机的工程设计提供了一定的参考.
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