Customized SRAM design for low power video code applications
- Resource Type
- Authors
- Kyungrak Choi; Jongsun Park; Sang Kyu Lee; Hoyoung Tang
- Source
- ISOCC
- Subject
- Decision support system
Hardware_MEMORYSTRUCTURES
FIFO (computing and electronics)
Computer science
business.industry
020208 electrical & electronic engineering
SIGNAL (programming language)
02 engineering and technology
Power (physics)
Embedded system
0202 electrical engineering, electronic engineering, information engineering
Code (cryptography)
Overhead (computing)
020201 artificial intelligence & image processing
Static random-access memory
Line (text file)
business
- Language
In this paper, an embedded SRAM architecture of Video application is proposed to reduce the power consumption. By analyzing the general read and write access patterns, the embedded memory is customized to reduce power consumption while achieving general FIFO operations. Some of the signal activations and the Pseudo-read operations are removed in FIFO. According to the simulation results with 65nm CMOS process, the proposed embedded memory for line buffer achieves 17.62% power savings with 3.72% overhead compared to the conventional embedded SRAM approaches.