Agradecimentos: The authors gratefully acknowledge support from Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) (Grant Nos. 2017/19862-3, 2019/16249-4, and 2015/14836-9), Conselho Nacional de Pesquisa e Desenvolvimento (CNPq) (Grant Nos. 407418/2018-0 and 303869/2018-6), to the Portuguese Foundation for Science and Technology (FCT/MCTES), through the UIDB/50008/2020 (Instituto de Telecomunicações, IT), national funds and when applicable co-funded EU funds by FEDER under the PT 2020 Partnership Agreement. The authors also thank Prof. Italo Odoni Mazali, who kindly allowed the rGO synthesizes in his laboratory, and Prof. Martin Taylor for the technical review of the manuscript and the fruitful discussions on these results Abstract: Multilayered self-assembled structures having different constituents are very appealing for preparing novel materials with unusual electrical phenomena not observed on the individual sheets. Here, the fabrication and characterization of aligned multilayered architectures comprised of reduced graphene oxide (rGO) and poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS), embedded into polymer electrolytes, are reported. The in-plane conductivity is five orders of magnitude higher than the cross-plane value, resulting in the highest anisotropic ratio reported to date for multilayer materials. Temperature-dependent measurements corroborate the high anisotropic electrical behavior, with charge transport weakly thermally activated (E-a = 33 meV) along the aligned conductive phases. Cross-plane charge transport fits well with the variable ranging hopping model, presenting an activation energy of 1.0 eV. Such a high anisotropic electrical behavior is explored in a novel transistor architecture where the anisotropic film operates simultaneously as a dielectric layer and as a transistor channel, with the cross-plane electric field modulating the in-plane conduction. The device shows ambipolar charge transport; however, the n-type carrier transport dominates the conduction with the field-effect mobility of 4.0 cm(2) V-1 s(-1). A simple and efficient way is presented to use electrical anisotropy to tailor transistors without a lattice mismatch at the dielectric/semiconductor interface FUNDAÇÃO DE AMPARO À PESQUISA DO ESTADO DE SÃO PAULO - FAPESP CONSELHO NACIONAL DE DESENVOLVIMENTO CIENTÍFICO E TECNOLÓGICO - CNPQ Fechado