Experimental Characterization and Simulation of Electron-Induced SEU in 45-nm CMOS Technology
- Resource Type
- Authors
- L. Gouyet; Robert Ecoffet; P. Pourrouquet; A. Samaras; Francoise Bezerra; N. Chatry; Eric Lorfevre; N. Sukhaseum; B. Vandevelde
- Source
- IEEE Transactions on Nuclear Science. 61:3055-3060
- Subject
- Physics
Nuclear and High Energy Physics
business.industry
Monte Carlo method
Hardware_PERFORMANCEANDRELIABILITY
Electron
Radiation
Upset
Computer Science::Hardware Architecture
Back end of line
Nuclear Energy and Engineering
CMOS
Single event upset
Cathode ray
Electronic engineering
Optoelectronics
Electrical and Electronic Engineering
business
- Language
- ISSN
- 1558-1578
0018-9499
This paper presents the single-event upset characterization of a commercial field programmable gate array (FPGA) using electron radiation. FPGA radiation test results under high energy electrons are described and the dependence between electron energy and SEU cross section is highlighted. A technological cross section is performed to evaluate the back end of line (BEOL) layers composition and thickness. These values are used to perform Monte Carlo simulations of the commercial FPGA exposed to 20-MeV primary electron beam. Calculation results show that electrons are able to generate SEU on the FPGA embedded RAM and confirmed experimental data. SEU rates induced by Jovian electrons are estimated using two different tools: Monte Carlo in GEANT4 and the OMERE Software.