5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application
- Resource Type
- Authors
- Taejoong Song; Hoyoung Tang; Jae-Seung Choi; Baeck Sang-Yeop; Lee Inhak; Dong-Wook Seo; Jongwook Kye
- Source
- VLSI Circuits
- Subject
- Very-large-scale integration
Input offset voltage
Computer science
business.industry
Electrical engineering
Hardware_PERFORMANCEANDRELIABILITY
Chip
Power (physics)
Reduction (complexity)
Hardware_INTEGRATEDCIRCUITS
Static random-access memory
business
5G
Voltage
- Language
Voltage Auto Tracking Cell Power Lowering (VACPL) Write Assist circuit is proposed for low-power SRAM with dual-rail architecture. VACPL adaptively controls the cell voltage with respect to the dual rail offset voltage to maximize bitcell write-ability. A 5nm EUV FinFET test chip demonstrates 210mV VMIN improvement and 4.7x larger range of operating voltage with VACPL. The proposed VACPL and VATA achieves 95.2% leakage power reduction by lowering VDDC by 400mV in 5nm 5G mobile device.