FPGA technology mapping with encoded libraries and staged priority cuts
- Resource Type
- Authors
- Val Pevzner; Kristofer Vorwerk; Arun Kundu; Andrew Kennings; Andy Fox
- Source
- ACM Transactions on Reconfigurable Technology and Systems. 4:1-17
- Subject
- General Computer Science
business.industry
Logic block
Computer science
Parallel computing
Simple (abstract algebra)
Mapping algorithm
Lookup table
Hardware_INTEGRATEDCIRCUITS
Electronic design automation
Technology mapping
business
Field-programmable gate array
Computer hardware
Hardware_LOGICDESIGN
Electronic circuit
- Language
- ISSN
- 1936-7414
1936-7406
Technology mapping is an important step in the FPGA CAD flow in which a network of simple gates is converted into a network of logic blocks. This article considers enhancements to a traditional LUT-based mapping algorithm for an FPGA comprised of logic blocks which implement only a subset of functions of up to k variables; specifically, the logic block is a partial LUT, but it possesses more inputs than a typical LUT. An analysis of the logic block is presented, and techniques for postmapping area recovery and timing-driven buffer insertion are also described. Numerical results are put forth which substantiate the efficacy of the proposed methods using real circuits mapped to a commercial FPGA architecture.