Gate Dielectric Damage Due To High-Tilt Implant.
- Resource Type
- Article
- Authors
- Felch, S. B.; Hung, R.; Ninan, B.; Smayling, M.; Toshiyuki, N.; Chen, H.; Chang, C.-P.
- Source
- AIP Conference Proceedings. 2006, Vol. 866 Issue 1, p516-519. 4p. 7 Graphs.
- Subject
- *DIELECTRICS
*CAPACITORS
*METAL oxide semiconductors
*ION implantation
*SILICON polymers
*BORON
*OXIDATION
*DIFFUSION
- Language
- ISSN
- 0094-243X
This paper reports an assessment of the gate dielectric damage caused by high-tilt implants using MOS capacitors fabricated with 50 Å SiO2 and doped polysilicon gates. Capacitor area, structure, and perimeter-to-area ratio were varied to enable identification of the implant damage contributions. The implants studied were typical PMOS source/drain extension conditions that would be used with a diffusion-less anneal. Tilt angles up to 40 degrees were evaluated. Current-voltage sweeps from 0V to -8V were performed to characterize the dielectric quality of the capacitors. Some results have confirmed expectations, as BF2 implants showed more damage than B implants of an equivalent energy. Additional data shows the dependence of the damage on tilt angle and polysilicon re-oxidation thickness. © 2006 American Institute of Physics [ABSTRACT FROM AUTHOR]