As standard planar transistors have reached their scaling limit new sophisticated architectures have found their way into mass production. One option is the Fully Depleted Silicon-on-Isolator (FDSOI) technology, which combines performance efficiency with a cost effective, planar architecture. Approximately, 75% of the process steps in FDSOI can be leveraged from the established 28 nm bulk technology, while there are certain process modules that require the introduction of new processes, i.e., low- k spacer deposition and the epitaxial growth of SiGe gate channels and Si:B, SiGe:B source/drain regions. In this article, we want to focus on the deposition of the low- k spacer, which provides low gate-to-drain capacitances. The standard SiN spacer was replaced by a SiBCN spacer. Electrical results show a clear 10% increase in ring-oscillator frequency. [ABSTRACT FROM AUTHOR]