The Panel level package (PLP) is gradually applied to some power devices due to its lower parasitic parameters, lower material cost, and higher packaging efficiency. In most application scenarios, the solder layer fatigues with temperature fluctuations. Thermal cycling life prediction is an important method for reliability analysis of the solder layers. At present, Darveaux model is commonly used to predict the thermal cycling life of the solder layers, but this model is inaccuracy in predicting the life of solder layers in the PLP. In this paper, the Darveaux model is optimized, and a new method for calculating the failure feature size is proposed, which improves the prediction accuracy of the solder layers life in the PLP from 77.75% to 95.05%.