A high-performance RISC-V co-processor architecture for fast IP processing
- Resource Type
- Conference
- Authors
- Kong, Xinjie; He, Weiliang; Han, Jun
- Source
- 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Solid-State & Integrated Circuit Technology (ICSICT), 2022 IEEE 16th International Conference on. :1-3 Oct, 2022
- Subject
- Components, Circuits, Devices and Systems
Integrated circuit technology
Costs
Hardware
IP networks
Coprocessors
- Language
Longest Prefix Matching (LPM) plays an important role in fast IP processing. In this paper, a hardware coprocessor architecture connected to high-performance RISC-V processor is proposed to achieve faster LPM search. By applying specific customized instructions to achieve HW/SW co-processing, we can gain 111% performance improvement for every search iteration. The implementation results under TSMC 28nm technology show that the proposed co-processor can work at 1GHz and only require 0.1% extra area cost (5056 um 2 ) compared to the whole system of the Xuantie processor.