The MDAC’s residue amplifier is the bottle neck of pipelined ADCs. By taking advantage of high gm and high ft of BJTs, BICMOS amplifier achieves higher closed-loop bandwidth and better settling behavior at high sampling rate. However, the gain of the residual amplifier may drop due to the low input impedance of BJTs. To solve the problem, a base current compensation technique is proposed in this paper to improve the open-loop gain and get better settling performance at high frequency. Also, dynamic biasing method is employed in the design to reduce power consumption. The proposed circuit is implemented in a 16bit 312.5Msps BICMOS pipelined ADC. By taking advantage of base current compensation technique, the SFDR of the ADC first stage output is over 95dBc with 2Vpp input signal at the frequency of 306MHz.