Automated Deep Learning Platform for Accelerated Analog Circuit Design
- Resource Type
- Conference
- Authors
- Dutta, Rahul; James, Ashish; Raju, Salahuddin; Jeon, Yong-Joon; Foo, Chuan Sheng; Tshun Chuan Chai, Kevin
- Source
- 2022 IEEE 35th International System-on-Chip Conference (SOCC) System-on-Chip Conference (SOCC), 2022 IEEE 35th International. :1-5 Sep, 2022
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineering Profession
Signal Processing and Analysis
Deep learning
Circuit optimization
Simulation
Training data
Artificial neural networks
Analog circuits
Routing
Computer aided design
integrated circuits
algorithms
analog circuit design
deep learning
neural networks
and optimization
- Language
- ISSN
- 2164-1706
We present an analog design framework for circuit sizing selection using neural networks. The proposed automated deep learning (ADL) platform uses neural networks (NN) as a differentiable surrogate model for circuit performance to model the nonlinear and high dimensional relationships between sizing performance and circuit performance in analog circuits. Gradient-based constrained optimization is then used to propose new sizing parameters for the desired design closure, which are then verified using EDA tools. If circuit performance falls short of desired performance, the simulation results from the EDA tools are also used as additional training data to update the neural network model for the next design iteration. The tight coupling between NN and EDA tools in an iterative design loop achieves multi-variate design closure and has the capability to synthesize circuits with a significantly reduced number of circuit simulations.