12-inch 90-nm Bipolar-CMOS-DMOS (BCD) process has attracted significant attention because of better device performance and lower cost. As in 12-inch process, wafer edge process control is more challenging, yield loss in BCD products is frequently detected. With layer-by-layer failure analysis, one fail mode is found that the wafer edge yield loss is due to Metal-1 (M1) to gate leakage in laterally double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistors. The influences of inter-layer-dielectric (ILD) thickness, M1 etch recipe, and LDMOS layout on the leakage were systematically studied. Based on the effort, a sequence of process optimizations have been applied, which help to improve the total production yield by 5-10%.